PCB Reverse Engineering #94

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opened 2025-09-25 22:43:14 +00:00 by rahix · 1 comment

rahix commented

2025-09-25 22:43:14 +00:00

Owner

The process of taking a physical PCB and extracting its layout and schematic for analysis and repair purposes.

We want to be able to perform this on modern high layer-count PCBs (e.g. 12 layer) using low-cost and approachable techniques.

ID Hiethieth0A

The process of taking a physical PCB and extracting its layout and schematic for analysis and repair purposes. We want to be able to perform this on modern high layer-count PCBs (e.g. 12 layer) using low-cost and approachable techniques. ID Hiethieth0A

forgejo-actions commented

2025-09-25 22:43:19 +00:00

Partial Techtree

flowchart BT

    classDef eoi fill:#fff, stroke:#000, color:#000;
    classDef dependant fill:#fff, stroke:#888, color:#888;
    classDef dep_missing fill:#fcc, stroke:#800, color:#000;
    classDef dep_assigned fill:#ffa, stroke:#a50, color:#000;
    classDef dep_completed fill:#afa, stroke:#080, color:#000;
    0:::eoi
    0["<a href='https://git.fa-fo.de/fafo/techtree/issues/94' target='_blank'>#94</a> | ASSIGNED<br/><i>Process</i><br/><b>PCB Reverse Engineering</b>"]
    1:::dep_assigned
    1["<a href='https://git.fa-fo.de/fafo/techtree/issues/89' target='_blank'>#89</a> | ASSIGNED<br/><i>Process</i><br/><b>PCB Delayering</b>"]
    2:::dep_missing
    2["<a href='https://git.fa-fo.de/fafo/techtree/issues/3' target='_blank'>#3</a> | MISSING<br/><i>Equipment</i><br/><b>Lapping Machine</b>"]
    3:::dependant
    3["<a href='https://git.fa-fo.de/fafo/techtree/issues/114' target='_blank'>#114</a> | MISSING<br/><i>Process</i><br/><b>Semiconductor & Electronics Analysis</b>"]
    0 --> 1
    1 --> 2
    3 --> 0

Digest: f85596d17361de55cdff33b97f95a722f3607ff357460b9256de99e83c2f14fd; Last Updated: 2025-11-09 09:56:09

## Partial Techtree ```mermaid flowchart BT classDef eoi fill:#fff, stroke:#000, color:#000; classDef dependant fill:#fff, stroke:#888, color:#888; classDef dep_missing fill:#fcc, stroke:#800, color:#000; classDef dep_assigned fill:#ffa, stroke:#a50, color:#000; classDef dep_completed fill:#afa, stroke:#080, color:#000; 0:::eoi 0["<a href='https://git.fa-fo.de/fafo/techtree/issues/94' target='_blank'>#94</a> | ASSIGNED Process PCB Reverse Engineering"] 1:::dep_assigned 1["<a href='https://git.fa-fo.de/fafo/techtree/issues/89' target='_blank'>#89</a> | ASSIGNED Process PCB Delayering"] 2:::dep_missing 2["<a href='https://git.fa-fo.de/fafo/techtree/issues/3' target='_blank'>#3</a> | MISSING Equipment Lapping Machine"] 3:::dependant 3["<a href='https://git.fa-fo.de/fafo/techtree/issues/114' target='_blank'>#114</a> | MISSING Process Semiconductor & Electronics Analysis"] 0 --> 1 1 --> 2 3 --> 0 ``` Digest: f85596d17361de55cdff33b97f95a722f3607ff357460b9256de99e83c2f14fd; Last Updated: 2025-11-09 09:56:09